Scope
We instrument worst-case ISR stacks, quantify tail latency, and propose coalescing patterns compatible with your safety story.
Included analyses
- GPIO vs DMA trigger comparison
- NVIC priority map with rationale
- FPU context save audit
- Motor PWM blanking window review
- Deferred bottom-half redesign sketches
Outcomes you can publish internally
- Tail latency histogram pack
- NVIC change list with rollback
- Bench harness for CI smoke
Lead advisor
Noah Lee
Systems validation lead for mixed-signal motion stacks.
FAQ
Hardware needed?
Two DUTs, logic analyzer, and safe mechanical limits for spin tests.
Functional safety?
We align with your existing hazard analysis; we do not replace it.
Noise concerns?
Shielding and grounding review is advisory only.
Experience notes
“They surfaced an SPI ISR that collided with our FOC loop—specific and actionable.”