Scope
We pair spectrum snapshots with thread timelines to show which stacks contribute to problematic harmonics, then propose firmware-side mitigations.
Included analyses
- Thread-to-clock enable matrix
- SPI clock slew experiments
- ADC sample window relocation plan
- Shield-can rework suggestions (advisory)
Outcomes you can publish internally
- Correlated timeline poster
- Mitigation experiment queue
- EMC retest script
Lead advisor
Jiwon Choi
RTOS performance engineer with RF-adjacent firmware experience.
FAQ
Chamber time?
We coordinate with your EMC partner; chamber fees are separate.
Hardware mods?
We document suggested changes; your EE approves fab spins.
Certification?
We do not certify; we supply evidence and hypotheses.
Experience notes
“The field noise docket tied a surprising harmonic to a debug UART re-enable.”