Scope
We profile cache line sharing, DMA coherence pitfalls, and MPU region overlaps, then deliver a patch-ready checklist.
Included analyses
- MPU region map with overlap scan
- DMA descriptor alignment audit
- Write-back vs write-through decision tree
- Benchmark harness for memcpy hotspots
Outcomes you can publish internally
- Alignment patch list
- MPU config diff
- Benchmark notebook
Lead advisor
Sora Kim
Benchmark analyst for memory-bound pipelines.
FAQ
Cortex-A scope?
Limited to MCU-class MPUs unless separately agreed.
Compiler versions?
We pin to the toolchain you ship; mismatches are flagged early.
Known limitation?
We cannot reverse engineer closed DMA engines without vendor support.
Experience notes
“DDR alignment and cache hygiene sprint clarified our DMA double-buffer mistake.”